The voltage in a digital circuit may be designed to vary between 0.0 and 1.2v. Any voltage below 0.5v is considered logic ‘0’, and any voltage above 0.7v is considered logic 1. Then the noise tolerance of 0 is a signal with a voltage value below 0.5v, and the noise tolerance of ‘1’ is a signal with a voltage value above 0.7v. Generally speaking, it is the allowable noise limit of the whole circuit.
The rated high level and low level of TTL circuit are 2.4v and 0.4v respectively, and the minimum identifiable level (i.e. critical identifiable level) is 2v and 0.8v. That is, the height level of the system is identified as 2.4v, but if a signal appears to be 2v voltage after being superposed by noise, it can also be identified as high level; Low level rated identification is 0.4v. If a signal shows 0.8v voltage after being superposed by noise, it can also be identified as low level. The noise tolerance of both high and low levels of TTL is 0.4v, which means that when the allowable noise swing/jitter superimposed on the signal level is less than 0.4v, it will not affect the correct identification of logic. The noise tolerance is the allowable noise amplitude margin superimposed on the signal level. The noise signal within the noise tolerance is allowable and will not affect the correct identification. The noise tolerance is 0.4v, which means that the signal level can be allowed to have noise superimposed with a margin of less than 0.4v. In this case, the noise tolerance is not measured as an absolute voltage, and there is no ratio. The noise tolerance of CMOS chips is usually larger than TTL, because VOH is closer to the power supply voltage, and the minimum value is closer to zero.
In communications systems engineering, noise tolerance is the rate at which a signal exceeds a very small acceptable amount. It is usually measured in decibels.
